Hardware Security Architect at Microsoft

Hardware Security Architect Details

Feb. 19, 2019, 6:29 p.m.
Hardware Engineering
Individual Contributor
Full-Time
Sunnyvale, WA
collaborative silicon team
Microsoft is a leader in design of world-class devices and silicon. Come join our dynamic and collaborative silicon team. We are looking for an architect to join a team of experienced hardware security architects to help grow this discipline and help make hardware devices more secure. The successful candidate will be a motivated self-starter who will thrive in this highly technical environment, is continually intellectually curious, collaborates beyond the tasks they own, to help us design products that are shaping the future of trusted computing. A candidate that has a mindset of thinking about unusual ways in which an adversary might be able to compromise a system will be successful.

Your job responsibility will be to continually advance the security of a wide spectrum of devices including IoT, consumer electronics, PCs and more, empowering people and devices to be ever more productive and trusted. Specify HW security modules at a low enough level to address security issues Evaluate systems of components to ensure security goals are maintained Prototype and evaluate algorithms and architecture using C/C++ based architectural models Work with other architects, designers, and verification teams to contribute, review, and provide feedback to relevant specifications and designs
Minimum Qualifications: BS/MS in Electrical, Computer Engineering, or Computer Science 4+ years of experience C/C++ coding experience Microarchitecture experience RTL experience including owning a design module Understanding of security mechanisms including confidentiality, integrity, and authentication Familiarity of cryptography and security standards Track record of team technical leadership and individual technical contribution on challenging projects Excellent communication skills Preferred Qualifications: Ownership and task completion through multiple phases of ASIC project architecture,
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