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Job Details
Posted date: Feb 26, 2026
Category: Silicon Engineering
Location: Mountain View, CA
Estimated salary: $188,900
Range: $119,800 - $258,000
Employment type: Full-Time
Work location type: 3 days / week in-office
Role: Individual Contributor
Description
OverviewDo you have a passion for advanced silicon signoff and physical verification at leading-edge technology nodes? You will be part of a team responsible for driving state-of-the-art Physical Verification CAD solutions for Microsoft’s silicon design teams. In this role, you will foster the enablement and support of advanced-node DRC, LVS, Antenna, and ESD signoff flows, working closely with EDA vendors, and internal design teams. You will own PV signoff methodology end to end, identify gaps, and drive scalable, production-ready solutions across multiple silicon programs. We are committed to a diverse and inclusive workspace and strongly encourage applicants from all backgrounds and walks of life. Difference makes us better.
Responsibilities
Develop, maintain, and support Physical Verification (PV) flows across all Silicon projects, spanning early design (shift-left) through final signoff, including DRC, LVS, ERC, antenna, and advanced checks.Own PV methodology, including guidelines, checklists, milestone definitions, and waiver strategies, ensuring consistent and predictable execution across programs and nodes. Partner closely with Physical Design teams to: Enable early PV runs o Debug complex DRC/LVS/ERC/PERC issues o Identify systemic design or flow gaps and drive fixes to closure. Lead resolution of PV-related flow and design issues, including tool stability, runtime scalability, deck integration, waiver correctness, and cross-tool debug.Drive cross-functional alignment with CAD, Technology, and external EDA partners (e.g.,Siemens, Synopsys) to communicate PV requirements, influence roadmap priorities, and unblock execution at critical project milestones.Support PDK and node enablement activities, ensuring PV flows are validated, production-ready, and aligned with foundry decks and internal signoff criteria across multiple technology variants.Contribute to PV activities, including training material, documentation, onboarding labs, and continuous improvement of automation and debug infrastructure.
Qualifications
Required Qualifications:
Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experienceOR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experienceOR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experienceOR equivalent experience.
Other Qualifications:
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
Preferred Qualifications:
Experience with industry-standard PV tools, such as Calibre. Scripting skills in at least one language (TCL, Python, Perl, or equivalent) for flow automation, debug, and data analysis. Ability to debug complex, cross-domain issues, reason about root cause (design vs flow vs tool), and drive issues to closure across teams.BS + 12 years / MS + 10 years of relevant experience.SVRF rule or deck development experience, including customization, enablement, or debug support.Experience with advanced verification checks, such as: o PERC (including custom or CNOD-based checks) o ESD, EOS, level-shifter, and reliability-focused verification. ·Exposure to shift-left PV methodologies, TCIC flows, and early-stage verification strategies that improve convergence and reduce late-stage surprises.Prior experience contributing to or leading PV, methodology councils, or multi-project enablement efforts.
Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $158,400 - $258,000 per year.
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
https://careers.microsoft.com/us/en/us-corporate-pay
This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.
Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.