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Job Details
Posted date: Dec 04, 2025
There have been 2 jobs posted with the title of Principal Physical Design Engineer all time at Microsoft.Category: Silicon Engineering
Location: Mountain View, CA
Estimated salary: $222,050
Range: $139,900 - $304,200
Employment type: Full-Time
Work location type: 3 days / week in-office
Role: Individual Contributor
Description
OverviewMicrosoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for a Principal Physical Design Engineer to help achieve that mission.
As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the AISiE team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for a Principal Physical Design Engineer for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.
We are looking for a Principal Physical Design Engineer to join the team.
Responsibilities
We are seeking a experienced Principal Physical Design Engineer to join our dynamic team. As a Principal Physical Design Engineer, you will be responsible for Physical Design tasks at block, sub-chip, and/or full-chip level.  The tasks will include Floorplanning, Synthesis, Placement, CTS and custom clocking, Routing, Static Timing, Physical Verification, Formal Equivalency, Power Efficiency, IR-Drop, and EM.  You may also be involved in Physical Design flow development/automation and evaluation of and recommendations for technology, IP, and vendor selection.
Lead the PnR convergence recipe development for designs in a subsystem/Subchip and lead the PnR convergence for designs within the subsystem/subchip.Collaborate with Architecture, design, and implementation teams to ensure that floorplan meets design requirements and constraints.Develop and implement methodologies and strategies to improve physical design efficiency and performance.Develop and implement methodologies and strategies to sign off blocks, subsystem/Subchip in the areas of static timing, physical verification, logics equivalence, low power verification and electromigration and IR drop.Conduct physical design reviews, identify and resolve design issues, and provide guidance to junior engineers.Work closely with cross-functional teams to drive project success and meet project milestones.Stay current with industry trends and emerging technologies to continuously improve physical design processes and methodologies.
Qualifications
Required Qualifications:
Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience.
Other Requirements:
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations.  As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.
Preferred Qualifications:
Bachelor's or Master’s in Electrical or Computer Engineering or related field with 12+ years of experience.Experience in tapeouts of complex ASICs in leading edge technology.10+ years of experience in floorplanning, physical design, and integration of semiconductor designs.Experience in physical design tools and methodologies such as Cadence Innovus, Synopsys DP, and Calibre.Good understanding of semiconductor design principles, methodologies, and tools.Track record of successfully leading physical design projects and delivering high-quality semiconductor products.Effective communication, teamwork, and leadership skills.Ability to work in a fast-paced and dynamic environment, and drive cross-functional collaboration.Good understanding of foundry tech files and rule decks.#SCHIE
Silicon Engineering IC5 - The typical base pay range for this role across the U.S. is USD $139,900 - $274,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $188,000 - $304,200 per year.
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
https://careers.microsoft.com/us/en/us-corporate-pay
This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.
Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.
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