Job Details
Posted date: Sep 04, 2025
There have been 9 jobs posted with the title of Principal Design Verification Engineer all time at Microsoft.There have been 9 Principal Design Verification Engineer jobs posted in the last month.
Category: Hardware Engineering
Location: Redmond, WA
Estimated salary: $222,050
Range: $139,900 - $304,200
Employment type: Full-Time
Travel amount: 25.0%
Work location type: Up to 50% work from home
Role: Individual Contributor
Description
Microsoft Azure is pioneering the fastest network in the public cloud, driving industries into a new era of advanced technology through high-speed cloud computing, artificial intelligence (AI), and machine learning (ML). Within Azure Core, our mission is to build foundational capabilities that empower sectors such as energy, agriculture, healthcare, and personal banking. Azure’s innovation has positioned Microsoft as a leader in the public cloud space, unlocking transformative potential through data-driven ecosystems and technological breakthroughs that shape the future for millions worldwide.As a Design Verification Engineer in Azure Core, you will lead a team of engineers in verifying complex hardware designs. You’ll define and execute verification plans, develop SystemVerilog testbenches using Universal Verification Methodology (UVM), and collaborate closely with firmware, software, and hardware teams across global sites. Your work will ensure the delivery of high-quality designs for Fully Programmable Gate Arrays (FPGAs) powering millions of cloud servers. This role offers a unique opportunity to strengthen your technical leadership, mentor engineers, and deepen your expertise in UVM. As part of a focused verification team, your contributions will be highly visible and impactful, with room to grow in alignment with your career goals.
Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.
• You will write design verification test cases by identifying new tools, test methodologies, and/or best practices that include elements such as success metrics and tracking systems and develop, review and execute test plans for complex or large sized scope feature areas or products and provide guidance to other engineers to execute test plans.• Generate or contribute to a single or multiple project implementation schedules and determine how changes to project schedules and proposed designs impact the hardware engineering aspects of products.
• Monitor project progress/status updates across teams and anticipates potential challenges, sharing details with key stakeholders as necessary (e.g., proactively resolve design issues, advise on resource requirements, and/or identify feasible alternatives).
• Advise others regarding the appropriate test requirements and improvements to be included in relevant, highly complex hardware designs and specifications and review documentation to help ensure that the appropriate test requirements and improvements are included in relevant hardware designs and specifications by applying an understanding of how complex features or products work under a variety of scenarios.
• Develop System Verilog based testbenches using Universal Verification Methodology (UVM) testbenches for use within block level and subsystem level test environments along with reusable, configurable verification components for use across verification teams and to be leveraged for future design verification applications and projects.
Qualifications
Required Qualifications:Bachelor’s Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 8+ years technical engineering experienceOR Master’s Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 7+ years technical engineering experienceOR equivalent experience.7+ years of experience in design verification using System Verilog and Universal Verification Methodology (UVM).7+ years of experience leading small engineering teams in design verification, including defining test requirements, developing schedules, assigning tasks, tracking progress, and providing technical guidance.3+ years of experience writing scripts using industry-standard scripting languages such as Python, Perl, Tool Command Language (Tcl), and Shell.Other Requirements:
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. Preferred Qualifications:
Bachelor's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 12+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 8+ years technical engineering experience OR Doctorate Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 5+ years technical engineering experience OR equivalent experience. 5 + years experience developing testbenches using Universal Verification Methodology (UVM)3+ years of experience implementing System Verilog assertions and functional coverage, implementation and closure.1+ year(s) of experience verifying designs for Fully Programmable Gate Arrays (FPGA) and adapting to evolving requirements to meet customer needs. Knowledgable in industry standard interfaces like PCIe, DDR, AMBA AXI is a plus.Experienced in RTL design and/or debug processes.Hardware Engineering IC5 - The typical base pay range for this role across the U.S. is USD $139,900 - $274,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $188,000 - $304,200 per year.
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: https://careers.microsoft.com/us/en/us-corporate-pay
Microsoft will accept applications for the role until September 18, 2025.
Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form.
Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work. #azurecorejobs
Check out other jobs at Microsoft.