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Job Details
Posted date: Oct 23, 2025
Category: Hardware Engineering
Location: Redmond, WA
Estimated salary: $158,000
Range: $100,600 - $215,400
Employment type: Full-Time
Travel amount: 25.0%
Work location type: 3 days / week in-office
Role: Individual Contributor
Description
Microsoft’s mission is to empower every person and every organization on the planet to achieve more. Join us to achieve this by building the world’s computer. The Artificial Intelligence Silicon Engineering team is seeking passionate, driven, and intellectually curious computer/electrical engineers to deliver premium-quality designs once considered impossible. We are responsible for delivering cutting-edge AI designs that can perform complex and high-performance functions in an extremely efficient manner.We are looking for a Design Verification Engineer II to work in the dynamic Microsoft Artificial Intelligence System on Chip (AISoC) Silicon team. The candidate must be a highly motivated self-starter who will thrive in this cutting-edge technical environment. You will be part of the design verification team, driving many facets of high performance, high bandwidth designs.
Perform pre-silicon verification for complex IP, including creating testplans, developing Universal Verification Methodology (UVM) components and environments, writing test cases, debugging failures to root cause issues, running and maintaining regression suites, and closing coverage. Interact with architects and design engineers to create testplans covering verification strategy, test requirements, and test environments for IP/SS/SOC level verification. Define verification strategy, requirements, test environments for IP/SS/SOC level verification. Create test-plans and write tests to provide complete features coverage. Develop and implement technical solutions to complex quality and design challenges. Develop verification components like scoreboards, sequences, constraints, assertions and functional coverage. Triage and debug testbench, simulation, and emulation fails. Develop Makefiles and scripts for verification infrastructure. Apply Agile development methodologies including code reviews, sprint planning, and frequent deployment. Collaborate with teams across sites and geographies.
Qualifications
Required Qualifications:Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 2+ years technical engineering experience OR equivalent experience.2+ years of Technical Engineering Experience with Universal Verification Methodology (UVM), System Verilog and Verification Fundamentals 2+ years of debugging RTL (Verilog) designs as well as simulation and/or emulation environments 2+ years experience with verification for product from definition to Silicon, including writing test plans, developing tests, debugging failures and coverage signoff in C/C++ and Universal Verification Methodology (UVM) 2+ years experience with scripting language such as Python or Perl or shell scripts. Other Requirements:
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. Preferred Qualifications
5+ years of design verification experience with Universal Verification Methodology (UVM), System Verilog and Verification Fundamental In depth knowledge of verification principles, testbenches, stimulus generation, and UVM based test environments Verification experience for an IP or SS or SOC related to CPUs, VPUs, GPUs, Tensor unit, or similar Knowledge of System Verilog class, constraints, coverage and assertions. Experience in scripting languages such as Python or Perl Hands-on experience in Formal property verification, formal verification of computational data path designs Silicon Engineering IC3 - The typical base pay range for this role across the U.S. is USD $100,600 - $199,000 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $131,400 - $215,400 per year.
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: US corporate pay information | Microsoft Careers
Microsoft will accept applications for the role until Oct 28th 2025.
Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form.
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