Microsoft is a highly innovative company that collaborates across disciplines to produce cutting edge technologies that change our world. Microsoft is seeking a highly motivated, FPGA and ASIC IP design engineer to help build innovative FPGA-based computing systems within a large design team. Well-designed hardware can deliver huge amounts of fine-grained parallelism; therefore, provide a very fast infrastructure and significantly accelerate many types of computations. Microsoft products touch the lives of millions of users daily. This opportunity provides a great channel for product impact at the cutting edge of high-performance computing. Candidate should have experience analyzing code performance and implementing parallel code structures to optimize performance. Candidate should have a strong desire to learn how software solutions can be used to develop FPGA and/or ASIC solutions for Microsoft's next generation of cloud servers and applications. The candidate will contribute to a team
Work with engineering teams to analyze software implementations. Identify and architect software code structures to target HLS (High Level Synthesis) tools for FPGAs and ASICs. Work with application groups to define, architect, develop, verify, and release IP logic blocks and acceleration solutions Develop, integration and debug IP blocks using a mixture of software and hardware languages. Simulation and hardware validation of large design, including lab debug and internal user support Deploy and maintain acceleration solutions to meet significant reliability and service level requirements Work
A solid computer engineering background (MS in electrical and/or computer engineering or equivalent degree preferred, BS required) 7+ years of experience with software and hardware systems design, experience analyzing and improving software performance in C++, C# and C. Experience working in a team environment, coaching and mentoring team members Desired skills and experience: High performance computing, parallel programming and experience optimizing algorithms for hardware architectures Expertise in compilation flows and/or FPGA CAD tool development a plus. FPGA development environment tools expertise,